Image sensors capture images using thousands to millions of pixels that are typically arranged in an array. FIG. 1 depicts a top view of a pixel commonly used in a CMOS image sensor in accordance with the prior art. Pixel 100 includes photodetector (PD) 102 that collects charge in response to incident light. Before the charge is read out of photodetector 102, an appropriate signal is applied to the gate (RG) of a reset transistor via contact 104 to reset a charge-to-voltage conversion region (FD) 106 to a known potential VDD. Charge is then transferred from the photodetector 102 to the charge-to-voltage conversion region 106 when a transfer transistor is enabled through the application of an appropriate signal to a transfer gate (TG) using contact 108. The charge-to-voltage conversion region 106 is used to convert the collected charge into a voltage.
A gate 110 of an amplifier transistor (SF) is connected via signal line 111 to charge-to-voltage conversion region 106. To transfer the voltage from the charge-to-voltage conversion region 106 to an output VOUT, an appropriate signal is applied to a gate of a row select transistor (RS) via contact 112. Activation of the row select transistor enables the amplifier transistor (SF), which in turn transfers the voltage from charge-to-voltage converter (FD) to VOUT. Shallow trench isolation regions (STI) surround the photodetector (PD) and the pixel 100 to electrically isolate the pixel from adjacent pixels in the image sensor. An n-type isolation layer 114 surrounds the STI regions, as will be described in more detail in conjunction with FIGS. 2 and 3.
FIG. 2 illustrates a cross-sectional schematic view along line A-A in FIG. 1 depicting the prior art pixel structure. Pixel 100 includes the transfer gate (TG), charge-to-voltage conversion region 106, and photodetector 102. The photodetector 102 is implemented as a pinned photodiode consisting of n+ pinning layer 200 and p-type storage region 202 formed within n-type layer 204. N-type layer 204 is disposed over substrate layer 206.
Shallow trench isolation regions (STI) 208 are formed laterally adjacent to opposite sides of photodetector 102 and surround the photodetector. STI 208 is also formed laterally adjacent to the charge-to-voltage conversion region 106, with the transfer gate (TG) positioned between photodetector 102 and charge-to-voltage conversion region 106. STI regions 208 include a trench formed in the n-type layer 204 that is filled with a dielectric material 210. The n-type isolation layer 114 surrounds the sidewalls and bottom of each trench. Isolation layer 114 is typically formed by implanting an n-type dopant into the sidewalls and bottoms of the trenches prior to filling the trenches with the dielectric material 210.
FIG. 3 depicts a cross-sectional schematic view along line B-B in FIG. 1 depicting the prior art pixel structure. STI regions 208 are formed laterally adjacent to and surrounding photodetector 102. STI region 208 is also formed laterally adjacent to charge-to-voltage conversion region 106. N-type isolation layer 114 surrounds the sidewalls and bottom of the trenches.
The shallow n+ implant of isolation layer 114 can cause the peripheral capacitance of the charge-to-voltage conversion region 106 to increase, and can cause higher dark current or point defects due to the p+/n+ diode junction formed by the n-type isolation layer and the p-type charge-to-voltage conversion region 106. In addition the n-type isolation layer 114 that is laterally adjacent to the one or more transistors in pixel 100, such as the amplifier transistor (SF), can reduce the effective width of the transistors. This can cause narrow channel effects and require the design of a wider transistor that in turn reduces the fill factor of the pixel.